The present invention relates generally to a solid-state imaging apparatus, a method of driving this solid-state imaging apparatus, and a camera system. More particularly, the present invention relates to a solid-state imaging apparatus constituted to add signal charges inside a charge transfer block, a method of driving this solid-state imaging apparatus, and a camera system that uses this solid-state imaging apparatus as an imaging device.
Recently, digital still cameras based particularly on CCD (Charge Coupled Device) imaging devices have come into widespread use. In order to prioritize resolution, some of these digital still cameras use CCD imaging devices based on a so-called all-pixel reading scheme in which the signal charges of all pixels are all read at once at the same time and the signal charge of each one pixel is transferred independently, while others use CCD imaging devices based on a so-called frame reading scheme in which the signal charges of the pixels on odd-number lines and on even-number lines are read alternately for each field and the signal charge of each pixel is transferred independently.
Referring to FIG. 24, there is shown a schematic diagram illustrating the above-mentioned frame reading operation. Shown in this figure is an example in which a color filter composed of 2 prime colors×2 arrays is used. Referring to FIG. 25, there is shown a timing chart illustrating the vertical sync timing of 4-phase vertical transfer clocks φV1 through φV4. Referring to FIG. 26, there is shown a timing chart illustrating the horizontal sync timing of these clocks.
Meanwhile, when performing automatic focus (AF) control, automatic white balance (AWB) control, or automatic exposure (AE) control for example, use of the same operating mode as taking still pictures poses disadvantage in the response speed of the automatic controllers supporting these automatic control operations. Especially, use of a CCD imaging device of high pixel density poses a problem of further retarding the response speed of the automatic controllers. Also, use of the same operating mode as taking still pictures when monitoring an subject image on a LCD (Liquid Crystal Display) monitor or the like poses a problem in obtaining a smooth motion picture because of the slow frame rate.
One way of enhancing the frame rate is to increase the data rate of the output signal of the CCD imaging device. However, increasing the output signal data rate requires the provision of a sampling rate converter. In addition, as the clock frequency rises, the power dissipation increases and the cost of parts used is pushed up. Further, a new problem such as deteriorated S/N ratios occurs. For these reasons, it is not desirable to employ the method of increasing the output signal data rate of the CCD imaging device.
On the other hand, there is a so-called line thinning-out operation in which a read pulse is applied in a predetermined iterative unit with respect to a read gate block for reading the signal charges from pixels to read the signals charges of only the pixels of certain lines and send the read signal charges to a vertical transfer block, thereby reducing the number of lines to be outputted to provide a faster imaging signal (namely increasing the frame rate).
FIG. 27 is a schematic diagram illustrating this line thinning-out operation. This diagram shows an example in which a color filter of 2 primary colors×2 arrays is used and the signal charges of only 2 pixels among 8 vertical pixels. FIG. 28 shows a vertical sync timing of 4-phase vertical transfer clocks φV1 through φV4. FIG. 29 shows a horizontal sync timing of these clocks. It should be noted that, for the first-phase vertical transfer clock φV1 and the third-phase vertical transfer clock φV3, 2 lines of φV1A/φV1B and φVA/φV3B are generated.
In this line thinning-out operation, 8 pixels along line (vertical direction) provide an iterative unit. The signal charges for only 2 of these 8 pixels are read. The read signal charges for 2 lines are vertically transferred within a horizontal blanking period, and then a packet containing signal charge and a packet containing no signal charge are added together. Consequently, the number of output lines becomes ¼ of that of the above-mentioned frame read operation, but the frame rate becomes four times as high. At this time, two lines of signal charges are added in the horizontal transfer block. Because of the addition of charged and free packets, the saturation signal charge quantity in the sensor block becomes equal to that obtained in the frame read operation.
Thus, the above-mentioned line thinning-out operation provides faster imaging signals without increasing the data rate. However, this line thinning-out operation inevitably reduces the number of output lines, thereby deteriorating picture quality, or a CCD imaging device having higher number of pixels requires to increase the number of output lines to be thinned out, further deteriorating picture quality.
Another method for increasing frame-rate is available for performing various automatic control operations such as AF, AWB, and AE or a monitor operation by means of an LCD monitoring for example. In this method, the frame rate is increased not by thinning the number of output lines, but by adding signal charges between pixels in the vertical transfer block (hereafter referred to as pixel addition) or adding signal charges between lines in the horizontal transfer block (hereafter referred to as line addition).
According to the above-mentioned method, pixel addition or the line addition reduces the number of output lines, so that picture quality can be enhanced and sensitivity can be increased better than that of the line thinning-out operation in which the signal charges of the lines that are not outputted are discarded.
Conversely, this method increases the charge quantity in the vertical transfer block or the horizontal transfer block, multiplying the number of pixels or the number of lines to be added (or mixed), so that, when a pixel is fully or nearly saturated, the signal charge overflows in the vertical transfer block or the horizontal transfer block. One way of solving this problem is to design the vertical transfer block or the horizontal transfer block so that the charge quantity which is a multicative number of pixels or lines to be added can be handled. However, such a design requires to raise the drive voltage of vertical or horizontal transfer clock, resulting in inevitable increase in power dissipation.
In the related art designed vertical or horizontal transfer block, the saturation signal charge quantity of the sensor block (or the pixel) is determined by the mode of pixel addition. Therefore, the saturation signal charge quantity of the sensor block in the mode for transferring the signal charge of each pixel independently becomes about 1/X, where X is the number of pixels to be added. However, reducing the saturation signal charge quantity of the sensor block deteriorates the characteristics such as S/N ratio and dynamic range, so that it is not desirable to perform such reduction especially in the mode of still picture imaging with picture quality prioritized.
In consideration of the above mentioned requirement, a solid-state imaging apparatus has been proposed (for example, Japanese Published Unexamined Patent Application No. Hei 5-91417) in which it is assumed that the line addition be performed in the horizontal transfer block. In the monitoring mode, the saturation signal charge quantity of the sensor block is set to about a half of the saturation signal charge quantity in the still picture mode, thereby preventing the signal charge added in the horizontal transfer block due to the line addition from overflowing.
As described, in the above-mentioned related technology, setting the saturation signal charge quantity of the sensor block in the monitoring mode to about a half of that in the still picture imaging mode can prevent the signal charge in the horizontal transfer block from overflowing due to the line addition. However, because the line addition is performed by line-transferring two lines of signal charges from the vertical transfer block to the horizontal transfer block within a horizontal blanking period, the following problems are posed.
Because the horizontal blanking period is a limited period of time, the line-transfer of two lines of signal charges within this limited horizontal blanking period requires doubling of the transfer rate. Raising the transfer rate twice as high means raising the frequency of the vertical transfer clock for driving the vertical transfer block. As the vertical transfer clock frequency increases, the handling charge amount in the vertical transfer block runs short due to propagation delay for example. This causes problems, such as signal charge overflow and unwanted radiation when the pixel is fully or nearly saturated.